1. Technical Field
The present invention relates generally to an improved data processing system, and in particular to a method and apparatus for testing a processor architecture. Still more particularly, the present invention provides a method and apparatus for testing logical partitions in a logically partitioned data processing system.
2. Description of Related Art
A logical partitioned (LPAR) functionality within a data processing system (platform) allows multiple copies of a single operating system (OS) or multiple heterogeneous operating systems to be simultaneously run on a single data processing system platform. A partition, within which an operating system image runs, is assigned a non-overlapping subset of the platform's resources. These platform allocable resources include one or more architecturally distinct processors with their interrupt management area, regions of system memory, and I/O adapter bus slots. The partition's resources are represented by the platform's firmware to the OS image.
Each distinct OS or image of an OS running within the platform is protected from each other such that software errors on one logical partition cannot affect the correct operation of any of the other partitions. This is provided by allocating a disjoint set of platform resources to be directly managed by each OS image and by providing mechanisms for ensuring that the various images cannot control any resources that have not been allocated to it. Furthermore, software errors in the control of an operating system's allocated resources are prevented from affecting the resources of any other image. Thus, each image of the OS (or each different OS) directly controls a distinct set of allocable resources within the platform.
In testing architectures for LPAR data processing systems, code is often loaded into a logical partition to test the hardware implementation of the processor architecture. This type of code is referred to as a random code generator or a random code generation image. Random code generation images are typically designed to generate random instruction streams to stress test the hardware implementation of the processor architecture. A random code generation image tends to corrupt it's own memory image or crash the logical partition on a frequent basis. Such a result is undesirable because the point of the test using the random code generation image is to verify that these types of actions have no effect beyond the boundary of the logical partition.
Therefore, it would be advantageous to have an improved method, apparatus, and computer instructions for testing hardware implementations in a logical partitioned data processing system.